Intel says that when its long-delayed 10-nanometer Cannon Lake chips finally arrive, they’ll be a “full generation ahead” of rivals Samsung and TMSC, thanks to “hyper scaling” that squeezes in twice as many transistors. That will yield CPUs with 25 percent more performance and 45 percent lower power use than its current Kaby Lake chips when they ship towards the end of 2017. Furthermore, Intel thinks the tech will keep Moore’s Law going and give it a 30 percent cost advantage over competitors like AMD.
These are bold words, particularly since its chief rival Samsung is already producing 10-nanometer chips like the Snapdragon 835, the world’s hottest mobile CPU. However, Intel says that while the chip trace sizes are the same, it has better feature density, letting it squeeze in twice as many transistors as chips from Samsung. That in turn produces smaller die sizes, which “allows Intel to continue the economics of Moore’s Law,” the company explains in a PowerPoint.
Down the road, Intel will also release enhanced 10-nanometer tech called 10+ and 10++. To be sure, that’s mostly marketing-speak that will help it keep consumer’s attention until 7-nanometer chips come along. However, the refinements will offer a further 15 percent performance and 30 percent efficiency boost, it says.
Intel laid out all this chip info as part of its Technology and Manufacturing Day (April 13, 2017), probably to sooth buyers and investors. Not only did Samsung and Qualcomm beat it to the punch for 10-nanometer chips, AMD also unveiled Ryzen processors that could eat into both its high- and low-end PC markets.
However, Intel sounds pretty confident about its next-gen chips and beyond. It’s planning on building 10-nanometer chips for three years before moving on to 7-nanometer tech, about the same cycle length as its current 14-nanometer chips. “We are always looking three generations –- seven to nine years — ahead,” says Intel Executive VP Stacy J. Smith. “Moore’s Law is not ending at any time we can see ahead of us.”